Joycee Mekie

Assistant Professor
Electrical Engineering
IIT Gandhinagar

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Joycee Mekie

Publications

Conference Papers

  1. A. Nandi, C.K. Jha and J. Mekie, “Tunable Inexact Subtractors for Division in Image Processing Applications,” 63rd IEEE International Midwest Symposium on Circuits and Systems 2020 Springfield, MA, USA (MWSCAS) [ accepted].
  2. J. Kumar, N. Surana, and J. Mekie, “A Low-Voltage Split Memory Architecture for Binary Neural Networks” Poster presentation at the 2020 IEEE International Symposium on Circuits & Systems, Seville, Spain, 5 pages [ accepted].
  3. C.K. Jha, K. Prasad, A. Tomar, and J. Mekie, “SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors,” Poster presentation at the 2020 IEEE International Symposium on Circuits & Systems, Seville, Spain, 5 pages [ accepted].
  4. C.K. Jha*, K. Prasad*, V. Srivastava, and J. Mekie, “FPAD: a Multistage Approximation Methodology for Designing Floating Point Approximate Dividers,” Lecture presentation at the 2020 IEEE International Symposium on Circuits & Systems, Seville, Spain, 5 pages [ accepted]. [* Equally Credited Authors ]
  5. N. Surana, M. Lavania, A. Barma, and J. Mekie, Robust and high-performance 12-T interlocked SRAM for in-memory computing. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1323-1326). IEEE.
  6. J. Kumar, N. Surana, and J. Mekie, A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks. In 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID) (pp. 177-182). IEEE.
  7. C.K. Jha, A. Nandi and J. Mekie. “Quality Tunable Approximate Adder for Low-Energy Image Processing Applications” 2019 IEEE International Conference on Electronics Circuits and Systems 2019 (ICECS), Genovo, Italy, 4 pages.
  8. A. Nandi, C.K. Jha and J. Mekie, “Should We Code Differently When Using Approximate Circuits?,” 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Bankok, Thailand, 2019, 4 pages.
  9. C. Jha and J. Mekie, “Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs,” 2019 22nd Euromicro Conference on Digital System Design (DSD), Kallithea, Greece, 2019, pp. 174-181.
  10. C. K. Jha and J. Mekie, “SEDA - Single Exact Dual Approximate Adders for Approximate Processors,” 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, USA, 2019, pp. 1-2.
  11. M. Lavania, N. Surana, I. Anand and J. Mekie, “Read-Decoupled Radiation Hardened RD-DICE SRAM Cell for Low-Power Space Applications,” 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi’an, China, 2019, pp. 1-3.
  12. D. Datta, P. Dewangan, N. Surana and J. Mekie, “Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search,” 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi’an, China, 2019, pp. 1-3.
  13. P. Bharti, N. Surana, J. Mekie, “Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications,” 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), 2019.
  14. S. Gupta. J. Mekie, “Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop,” 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), 2019.
  15. S. A. Aketi, J Mekie, H. Shah, “Single-error hardened and multiple-error tolerant guarded dual modular redundancy technique,” 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018.
  16. J. Mekie, P. Mukim and K. Kale, “Impact of variations on synchronizer performance: an experimental study,” 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018.
  17. N. Surana, J. Mekie and N. Mohapatra, “Impact of high-κ spacer on circuit level performance of junctionless FinFET,” International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2017.
  18. N. Kumari and J. Mekie, “Upset hardened latch as data synchronizer,” International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2017.
  19. S. N. Ved, A. Arya, A. Bhange and J. Mekie, “A Comparative Study of Input Port and Crossbar Configurations in NoC Router Microarchitectures,” IEEE International conference on Signal Processing and Integrated Networks (SPIN), Feb 2017
  20. S.N. Ved, A. Arya, A. Bhange and J. Mekie, “Route-on-Fly: A Single Cycle Router,” IEEE International conference on Signal Processing and Integrated Networks (SPIN), Feb 2017
  21. S.N. Ved, A. Gour, A. Arya and J. Mekie, “Route-on-Fly: A Single Cycle Router,” IEEE International conference on Emerging Electronics (ICEE), Dec 2016
  22. N. Surana, A. Soni, A. Umap, J. Mekie, and S. Chaudhuri, “Asymmetrically Doped FinFET for Low-Power Analog Applications,” IEEE International conference on Emerging Electronics (ICEE), Dec 2016
  23. N. Surana, R. Kaur and J. Mekie, “Short and Deep Drain MOSFET for Space Applications: Device and Circuit Level Analysis,” IEEE International conference on Radiation effects on Electronic Components and Systems( RADECS), Sept 2016
  24. R. Kaur, N. Surana and J. Mekie, “Guarded Dual Rail Logic for Soft Error Tolerant Standard Cell Library,” IEEE International conference on Radiation effects on Electronic Components and Systems( RADECS), Sept 2016
  25. S. Teja, J. Mekie, J. Cabibihan N. Thakor and S. L. Kukreja , Fault Tolerant Tactile Sensor Arrays for Prosthesis, IEEE RAS/EMBS International Conference on Biomedical Robotics and Biomechatronic, June 2016
  26. J. Mekie, “Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-Clocked Systems”, in 20th IEEE International symposium on Asynchronous Circuits and Systems (ASYNC 2014), Germany, May 2014
  27. J. Mekie, S. Chakraborty, G. Venkataramani, P. Thiagarajan and D. K. Sharma, March 2006, “Interface Design for Rationally Clocked GALS Systems,” in Proc. of ASYNC, pp. 160-171.
  28. J. Mekie, S. Chakraborty and D. K. Sharma, Jan 2004, “Evaluation of Pausible Clocking Scheme for Interfacing High Speed IP Cores in GALS Framework,” in Proc. of International Conference on VLSI Design, pp. 559-564.
  29. S. Chakraborty, J. Mekie and D. K. Sharma, Sept 2003, “Reasoning about Synchronization Issues in GALS Systems: A Unified Approach,” invited paper in Proc. of Workshop on Formal Methods in GALS Architectures (FMGALS), Formal Methods Europe Symposium.

Journals

  1. C.K. Jha*, I. Doshi* and J. Mekie, “Analysis of Worst-Case Data Dependent Temporal Approximation in Floating Point Units” IEEE Transactions on Circuits and Systems II: Express Briefs [ accepted]. [* Equally Credited Authors ]
  2. Aketi, S. A., Gupta, S., Cheng, H., Mekie, J., & Beerel, P. A. (2020). SERAD: Soft Error Resilient Asynchronous Design using a bundled data protocol. IEEE Transactions on Circuits and Systems I: Regular Papers (2020)
  3. P. K. Bharti, N. Surana and J. Mekie, “Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder,” in IET Computers & Digital Techniques, vol. 13, no.6, pp. 505-513, 2019.
  4. Surana, Neelam, Pramod Bharti, and Joycee Mekie. “Hetro8T: Power and Area Efficient ApproximateHeterogeneous 8T SRAM for H. 264 Video Decoder.” IET Computers & Digital Techniques (2019).
  5. Ved, Sneha N., Sarabjeet Singh, and Joycee Mekie. “PANE: Pluggable asynchronous network-on-chip simulator.” ACM Journal on Emerging Technologies in Computing Systems (JETC) 15.1 (2019): 7.
  6. Jha, Chandan Kumar, et al. “Energy and error analysis framework for approximate computing in mobile applications.” IEEE Transactions on Circuits and Systems II: Express Briefs (2019).
  7. Surana, Neelam, and Joycee Mekie. “Energy efficient single-ended 6-T SRAM for multimedia applications.” IEEE Transactions on Circuits and Systems II: Express Briefs 66.6 (2018): 1023-1027. Reasoning about Synchronization using Abstract Timing Diagrams

Oral/Poster Presentations at International conferences and workshops

  1. P. Mukim, K. Kale and J Mekie, “Impact of Variations on Synchronizer Performance: An Experimental Study,” Fresh-ideas paper IEEE International symposium of Asynchronous circuits and systems, Brazil, May 2016
  2. Fathima Sinin and J. Mekie, “Comparative study of synchronizer circuits,” Fresh-ideas paper IEEE International symposium of Asynchronous circuits and systems, Brazil, May 2016
  3. J. Mekie, “Interfacing solutions for Globally asynchronous locally synchronous designs,” invited talk at Innovations for High Performance (iHP), Germany, May 2014
  4. J. Mekie, “Building new generation chips using asynchronous logic,” poster presentation at Intel Asia Innovation Summit, Taiwan, Nov 2014
  5. J. Mekie and Ved, Sneha, “Network on Chips: The Journey Overview”, in 27th International Conference on VLSI Design, Indian Institute of Technology Bombay, Mumbai, IN, Jan. 5-9, 2014
  6. J. Mekie, “Globally asynchronous, Locally-synchronous Designs,” invited talk at IEEE Indicon, Mumbai, Dec 2013
  7. J. Mekie, G. Samuel, S. Garg and S. Chakraborty, “Reasoning about timing in multi-cocked systems: A tool demo” tutorial, 3rd Workshop on Formal Methods in Safety Critical and Industrial Applications, IIT Bombay, June 2005

Book Chapters

  1. Mekie, Joycee, et al. “Interface design for rationally clocked GALS systems.” 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’06). IEEE, 2006.